In the prior art, a first phase-locked loop for generating a first clock signal includes a first phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a first frequency divider. The first phase frequency detector receives a first reference signal and a first feedback signal, and compares the first reference signal with the first feedback signal to generate a first comparison result signal. The first comparison result signal is converted into the first clock signal through the charge pump, the loop filter and the voltage controlled oscillator in turn. The first frequency divider has a first frequency divisor, and generates the first feedback signal according to the first frequency divisor and the first clock signal.
In the prior art, a second phase-locked loop for generating a second clock signal includes a second phase frequency detector, a control unit, a digitally-controlled oscillator and a second frequency divider. The second phase frequency detector receives a second reference signal and a second feedback signal, compares the second reference signal with the second feedback signal to generate a second comparison result signal. The control unit generates a digital adjustment signal according to the second comparison result signal. The digitally-controlled oscillator generates the second clock signal according to the digital adjustment signal. The second frequency divider has a second frequency divisor, and generates the second feedback signal according to the second frequency divisor and the second clock signal.
A technical scheme in the prior art disclosed in TW Patent No. M241,888 provides a counter-based all-digital clock multiplier.
Regarding the clock generating schemes in the prior art, it is necessary for most schemes thereof to utilize the digitally-controlled oscillator (DCO) or the voltage controlled oscillator (VCO) to make the frequency adjustment. In general, on some applications, it seems that the digitally-controlled oscillator or the voltage controlled oscillator is too complex on the hardware structure due to the frequency acquisition and the locking mechanism. Additionally, most of the clock generating schemes in the prior art employ the architecture having a single digitally-controlled oscillator or a single voltage controlled oscillator, and thus it seems that the schemes are not so flexible in the application of the multi-rate clock domain design.